A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value that represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. The inverters act as a latch that stores the data bit therein, so long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bitlines (i.e., a bitline true and bitline complementary). Other SRAM call designs may include a different number of transistors (e.g., 4T, 8T, etc.).
In the SRAM, a sense amplifier senses low power signals from the bitline and amplifies a small voltage swing to recognizable logic levels so that the data can be interpreted properly by logic outside of the memory. In SRAM operation, in order to read a bit from a particular memory cell a wordline along the particular memory cell's row is turned on, which activates all of the cells in a row. The stored value (0 or 1) from the particular memory cell is then sent to the bitline associated with the particular memory cell. The sense amplifier at the end of two complimentary bitlines amplifies the small voltages to a normal logic level. The bit from the desired cell is then latched from the particular memory cell's sense amplifier into a buffer, and placed on an output bus.
In SRAM, though, bit-line capacitance tends to be critical for performance. For example, lower capacitance of the bit-line will result in improved access times. However, as advanced nodes become smaller, the reduction in bit-line capacitance is becoming more challenging.